1. Field of the Invention.
The invention relates to the field of digital (binary) adders, particularly those employing carry lookahead.
2. Prior Art.
Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums that a user is conscious of, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, the carry bit that results from the addition of the lesser significant bits must be considered. This can easily be done by rippling a carry signal as the addition is performed. A problem with this, particularly for large words (e.g., 32 bits) is that substantial time is required to ripple the carry signal through the entire addition chain. And since the adders are often performing logic functions in critical time paths, the time needed to ripple the carry signal can slow up the microprocessor. This problem is dealt with in the prior art with carry lookahead circuits, skip-carry circuits and with different partitioning of group circuitry. These topics are discussed in U.S. Pat. No. 4,737,926.
The present invention is an improved carry lookahead adder in that fewer delays are encountered along critical paths in the adder. The adder therefore provides substantial improvement in terms of speed of operation when compared to prior art adders. Moreover, full adders which are often cascaded in prior art adders to form groups, are replaced with a novel circuit which develops intermediate carries.
The adder of the present invention is an improvement of an adder currently used in the Intel 386 microprocessor.